The present invention relates to field effect transistor (FET) devices, and more specifically, to local interconnects for FET devices.
FET devices such as, for example, planar FETs, multi-gate FETs, tri-gate FETs, and FinFETs may be arranged on a substrate having a number of FET devices. The source and drain regions of the devices may be electrically connected by conductive interconnects. In this regard, FIG. 1 illustrates a top view of a prior art example of an arrangement of fin FET devices 102a-h each having a source region (104a, 104b, . . . , 104h) and a drain region (106a, 106b, . . . , 106h) defined by fins 108. A gate stack 110 is arranged over the fins 102. A first conductive local interconnect (interconnect) 112 is arranged in contact with each of the source regions 104a, 104b, . . . , 104h and a second conductive local interconnect 114 is arranged in contact with each of the drain regions 106a, 106b, . . . , 106h. A conductive via 116 is arranged proximate to a distal end of the first conductive local interconnect 112 and a conductive via 118 is arranged proximate to a distal end of the second conductive local interconnect 114. The vias 116 and 118 may be connected electrically to other circuitry or features to provide a voltage at the vias 116 and 118. A conductive via 120 is arranged in contact with the gate stack 110.